Verification component reuse very important for SoC development projects as verification is consuming upto 80% of product development cycle. Conventional testbench co-simulation slows down emulation speed allowing only 10X improvement over simulation. Transaction based testbenches can improve speed upto 400X improvement over same simulation environment. Performance of co-simulation mandates use of transaction based interfaces for all verification environments.Mentor Veloce Emulator offers a proprietary transaction based acceleration technology (TBX – with xRTL instead of system verilog) which allows developers to write code that can be directly emulated with veloce. Veloce implements Accelera SCE-MI 2.0 and extends more portions in Emulator HW for acceleration. It also includes interface elements critical to high-bandwidth communication between Emulator & Host platform running Testbench application or software.
Downside of Mentor TBX is that TBX is not industry standard language & Verification Engineers have to learn yet another language. OVM offers libraries that allow System Verilog verification IPs to be interfaced with Emulators using SCE-MI2.0 standard interface libraries.
OVM – Open Verification Methodology is open standards specifications, based on IEEE std. 1800 2005 Systen Verilog standard. OVM provides a methodology & accompanying library for verification professionals.
