EVE duelling Mentor Patent Analysis

Mentor Strikes EVE with Fred Reblewski’s yet another patent #6,876,962. The patent was issued in 2005. And Mentor is seeking damages and to bar sale of EVE’s products in USA. Last Month, Mentor had similar suit in Japan against EVE.

This lawsuit reminds me of Mentor feuding over Cadence Quickturn, when Zycad/ Quickturn decade long feuds fueled court battles. Cadence took away emulation marketshare from Mentor back then. Is Mentor scared of EVE this time?

The patent is covering emulation of several designs concurrently. Emulation system consists of emulator with resources, and host system that generates netlists using available emulation resources & allows running multiple designs concurrently. As designs grow very large, emulation systems may cost several Million dollars to companies. Once companies buy the equipment, they want to make sure emulation resources are utilized effectively. One desired way is to allow regressing emulation of several designs concurrently. So the technology solves a unique problem for the industry and patent is valuable.

In July 2009, EVE launched its 1B gate Zebu Server, which offers easy setup and debugging to users. Zebu compiler can automatically handle designs of high complexity easily. With flexibility, multi-MHz performance, &  price/ performance Zebu servers are very competitive in the industry with no answer from Mentor at the time.

PR: Mentor Veloce Emulator with TBX for Simulation Acceleration

Verification component reuse very important for SoC development projects as verification is consuming upto 80% of product development cycle. Conventional testbench co-simulation slows down emulation speed allowing only 10X improvement over simulation. Transaction based testbenches can improve speed upto 400X improvement over same simulation environment. Performance of co-simulation mandates use of transaction based interfaces for all verification environments.

Mentor Veloce Emulator offers a proprietary transaction based acceleration technology (TBX – with xRTL instead of system verilog) which allows developers to write code that can be directly emulated with veloce. Veloce implements Accelera SCE-MI 2.0 and extends more portions in Emulator HW for acceleration. It also includes interface elements critical to high-bandwidth communication between Emulator & Host platform running Testbench application or software.

Downside of Mentor TBX is that TBX is not industry standard language & Verification Engineers have to learn yet another language. OVM offers libraries that allow System Verilog verification IPs to be interfaced with Emulators using SCE-MI2.0 standard interface libraries.

OVM – Open Verification Methodology is open standards specifications, based on IEEE std. 1800 2005 Systen Verilog standard. OVM provides a methodology & accompanying library for verification professionals.

Cadence Palladium XP Emulators Introduction

Cadence Design Systems released the Palladium XP near End of April 2010. Palladium XP is primarily Hardware Emulation Platform but unifies Simulation, Acceleration & Emulation in a single platform.

Features:
* Capacity – designs up to 2 Billion Gates
* Performance – upto 4 MHz
* Multi-domain/ users – Up to 512 users simultaneously
* Power Analysis –
* Metric Driven Verification -
* Embedded systems
* Highly Scalable
* Simulation Back Annotation – High fidelity representation of design so designers can quickly locate & fix bugs. Design teams can "hot-swap" simulation with acceleration & emulation.
* Configurations – XL for design teams, GXL for enterprise-class global teams

FPGA challenges

Commercial Emulators offer a good End-to-end solution (Software as main strength) for enabling faster models comparable to FPGA speeds (much slower). Emulators often have inbuilt FPGA boards or custom technologies (processors in Cadence Palladium).

FPGA prototyping has following limitations which make these time consuming. Validation teams working with complex designs or unstable designs have to plan several months & resources to make FPGA prototyping systems.
* Place & Routing - for designs spanning multiple FPGAs place & routing is hard
* Number of pins limitations on FPGAs, proprietary solutions offer work around but at expense of speed
* Design readiness - unstable and FPGA unfriendly code in RTL makes bring up extremely hard. Unready design blocks make it very difficult

Synopsys HAPS

More and more engineers are getting interested in Emulation or FPGA based validation acceleration tools and methodologies due to several reasons, including improvements in tools capabilities to handle large designs on FPGAs/ Emulators. Emulators offer better control, operability and synthesis than raw FPGAs, and every engineer loves "ease of use" for the tools to meet Time to Market pressures with given design complexity. FPGAs are far less expensive and are much faster than comparative Emulator solutions.

Here are some strengths offered by Synopsys HAPs, making it suitable for Product teams to deploy for projects.
* High Capacity - Synopsys HAPS technology offers somewhere in middle of Emulation & raw FPGA board solutions. Synopsys offers family of Xilinx FPGA (Virtex-6) boards that can be plugged and expanded for system needs.
* Tools for setup: Automated tools for System Setup, Synthesis, Partitioning, Initialization, Control, Debug
* Daughter cards for commons IO interfaces such as USB, DDR2, HDMI link etc
* Gate capacity ~5M gates/ board. Typical 25-75MHz system clocks (peak = 200MHz)
* Power/ Thermals/ Signal Integrity with 40 Layer board design & custom connectors
* Partitioning: With FPGAs there is inherent problem with design partitioning across multiple FPGAs due to pin limitations. Various techniques of pin multiplexing are used such as time multiplexing (penalty on speed). Pins are modeled as LVDS IOs running upto 1Gbit/s differential pairs instead of Virtex-6 fast serdes resources. This approach gives 128x1 signal per pair multiplexing giving overall 7X increase in # pins on FPGAs.
* Co-RTL simulation – implementation of event driven interfaces over UMRBus, co-simulate HAPs with VCS or other RTL simulators on the host. * UMRBus - HAPS boards are connected together over UMRBus – High speed link (Universal Multi-Resource Bus). UMRBus is used to connect to Host Platforms as well.
* Co-System Simulation -- SCE-MI 2.0 interface over UMRBus allowing testbenches & behavioral models in C/C++, SystemC, TLM2.0
* Synopsys DesignWare IP models are pre-tested on HAPS emulator, allowing architects to quickly put together models.

Overall I believe HAPS is great for SoC projects where each chip is ~5Million gates to fit on single board. I won't deploy HAPS for really large designs of such as 200Mgates. Synopsys tools for synthesis, partitioning, Designware ready IPs, Debug etc make the tool very cost effective as compared to Emulation.

C to FPGA technology

For a system designer, its often desired to add Hardware Acceleration to their code. C to FPGA can be a power technology aid to system designers, SW developers & even HW engineers validating their designs. There are commercial compilers available such as from Impulse technologies, that let a system designers quickly create FPGA compatible code for their designs.

 

C to FPGA is still in infancy & is used for custom applications. I haven't come across a known ASIC company deploying large scale ASIC design using C to FPGA as on going methodology. But technology is very promising and has found initial usage with big impact.

 

Applications where a system designer may need Hardware solution?

Here are some examples I pulled together to show where C to FPGA is deployed:

 

Financial Analytics:

* For a custom workload for example in Wall-street a company wants to quickly apply highly sophisticated algorithms to live stream data, algorithm developers often rely on CPU power to crunch the data quickly. Its possible to create FPGA based custom offload engines, where dedicated hardware engine can give edge to traders or trading companies.

There are several other dedicated custom hardware needs for following applications:

 

* Image and video processing; Video decoding; Fractal image generation; DSP filters

* Bioinformatics search algorithms

* Embedded processor acceleration

 

Todo: I'll add several use cases in future where C to FPGA technology can be deployed

 

Tools available to enable C to FPGA:

 

Synopsys validation tools

Synopsys provides a comprehensive portfolio of system-level products that bridge the gap from system design to implementation.

 

VCS: A popular RTL simulator, allows designers to simulate block level, full-chip, system level simulation models & verify designs before sending designs to fabrication.

Some of random test vector generation tools such as Specman can be co-simulated with VCS to find corner case/ random bugs in the design.

VCS also allows co-simulation of SystemC/ C++/ TLM2.0 models

 

Innovator: Innovator platform came from Synopsys Virtio acquisition.  Innovator allows system designers and software developers to quickly create fast Simulation models much before low level RTL designs are available or Si is available for SW developers to validate their SW with HW models called "virtual platforms". Innovator can help reduce overall development cycle as SW co-validation can start very early in development cycle.

 

CoMET/METoer -

 

Emulation: Synopsys offers HAPs platforms for FPGA based acceleration. Other commercial emulators from Mentor, Cadence, EVE can be used in validation environement.

 

Platform Architect: Platform architect provides rich set of SystemC/ TLM models useful for Co-simulation with Innovator or FPGA Emulation