Verification component reuse very important for SoC development projects as verification is consuming upto 80% of product development cycle. Conventional testbench co-simulation slows down emulation speed allowing only 10X improvement over simulation. Transaction based testbenches can improve speed upto 400X improvement over same simulation environment. Performance of co-simulation mandates use of transaction based interfaces for all verification environments.Mentor Veloce Emulator offers a proprietary transaction based acceleration technology (TBX – with xRTL instead of system verilog) which allows developers to write code that can be directly emulated with veloce. Veloce implements Accelera SCE-MI 2.0 and extends more portions in Emulator HW for acceleration. It also includes interface elements critical to high-bandwidth communication between Emulator & Host platform running Testbench application or software.
Downside of Mentor TBX is that TBX is not industry standard language & Verification Engineers have to learn yet another language. OVM offers libraries that allow System Verilog verification IPs to be interfaced with Emulators using SCE-MI2.0 standard interface libraries.
OVM – Open Verification Methodology is open standards specifications, based on IEEE std. 1800 2005 Systen Verilog standard. OVM provides a methodology & accompanying library for verification professionals.
While we appreciate the mention of our market leading, transaction-based accelerated verification solutions, we offer the following clarification to the post.
ReplyDeleteMentor's transaction-based acceleration product “TestBench XPress (TBX)” is entirely based on industry standards.
Being fully standards compliant, TBX offers interoperability with standards compliant software simulators like Mentor’s Questa. This allows users to maintain a single verification environment (testbench and DUT) for simulation and acceleration using TBX.
TBX allows communication between untimed testbenches running on a Host PC and timed RTL running on Veloce via a SCE-MI 2.0 compliant communication channel. One can use SystemVerilog DPI based function calls, SCE-MI 2.0 pipes, Virtual Interface, and/or TLM FIFOs for testbench and DUT communications.
xRTL is not a new proprietry language but 100% subset of behavioral SystemVerilog for efficient and optimal modeling of timed test-bench components. The xRTL compiler synthesizes the most commonly used SystemVerilog behavioral subset. This subset enables efficient and optimal emulation friendly modeling of transactors. This synthesizable SystemVerilog portion of the testbench is then accelerated by mapping it into Veloce along with the design under test.
In summary, TBX does not use any proprietary modeling language, is fully interoperable with standards compliant software simulators, and allows acceleration of a major portion of the testbench along with the DUT.
Vijay Chobisa
Product Marketing Manager
Mentor Graphics Corp. - Emulation Division