Synopsys HAPS

More and more engineers are getting interested in Emulation or FPGA based validation acceleration tools and methodologies due to several reasons, including improvements in tools capabilities to handle large designs on FPGAs/ Emulators. Emulators offer better control, operability and synthesis than raw FPGAs, and every engineer loves "ease of use" for the tools to meet Time to Market pressures with given design complexity. FPGAs are far less expensive and are much faster than comparative Emulator solutions.

Here are some strengths offered by Synopsys HAPs, making it suitable for Product teams to deploy for projects.
* High Capacity - Synopsys HAPS technology offers somewhere in middle of Emulation & raw FPGA board solutions. Synopsys offers family of Xilinx FPGA (Virtex-6) boards that can be plugged and expanded for system needs.
* Tools for setup: Automated tools for System Setup, Synthesis, Partitioning, Initialization, Control, Debug
* Daughter cards for commons IO interfaces such as USB, DDR2, HDMI link etc
* Gate capacity ~5M gates/ board. Typical 25-75MHz system clocks (peak = 200MHz)
* Power/ Thermals/ Signal Integrity with 40 Layer board design & custom connectors
* Partitioning: With FPGAs there is inherent problem with design partitioning across multiple FPGAs due to pin limitations. Various techniques of pin multiplexing are used such as time multiplexing (penalty on speed). Pins are modeled as LVDS IOs running upto 1Gbit/s differential pairs instead of Virtex-6 fast serdes resources. This approach gives 128x1 signal per pair multiplexing giving overall 7X increase in # pins on FPGAs.
* Co-RTL simulation – implementation of event driven interfaces over UMRBus, co-simulate HAPs with VCS or other RTL simulators on the host. * UMRBus - HAPS boards are connected together over UMRBus – High speed link (Universal Multi-Resource Bus). UMRBus is used to connect to Host Platforms as well.
* Co-System Simulation -- SCE-MI 2.0 interface over UMRBus allowing testbenches & behavioral models in C/C++, SystemC, TLM2.0
* Synopsys DesignWare IP models are pre-tested on HAPS emulator, allowing architects to quickly put together models.

Overall I believe HAPS is great for SoC projects where each chip is ~5Million gates to fit on single board. I won't deploy HAPS for really large designs of such as 200Mgates. Synopsys tools for synthesis, partitioning, Designware ready IPs, Debug etc make the tool very cost effective as compared to Emulation.