Synopsys validation tools

Synopsys provides a comprehensive portfolio of system-level products that bridge the gap from system design to implementation.

 

VCS: A popular RTL simulator, allows designers to simulate block level, full-chip, system level simulation models & verify designs before sending designs to fabrication.

Some of random test vector generation tools such as Specman can be co-simulated with VCS to find corner case/ random bugs in the design.

VCS also allows co-simulation of SystemC/ C++/ TLM2.0 models

 

Innovator: Innovator platform came from Synopsys Virtio acquisition.  Innovator allows system designers and software developers to quickly create fast Simulation models much before low level RTL designs are available or Si is available for SW developers to validate their SW with HW models called "virtual platforms". Innovator can help reduce overall development cycle as SW co-validation can start very early in development cycle.

 

CoMET/METoer -

 

Emulation: Synopsys offers HAPs platforms for FPGA based acceleration. Other commercial emulators from Mentor, Cadence, EVE can be used in validation environement.

 

Platform Architect: Platform architect provides rich set of SystemC/ TLM models useful for Co-simulation with Innovator or FPGA Emulation